1. Technical Field
The present invention relates in general to an improved data processing system and in particular to an improved method and system for speculatively issuing instructions in a data processing system. Still more particularly, the present invention relates to an improved method and system for speculatively issuing instructions in a data processing system which are dependent upon data from previously executed instructions for which a result is expected within n clock cycles.
2. Description of the Related Art
In modern microprocessors, it is advantageous to support speculative execution of instruction using branch prediction mechanisms, out-of-order execution, and multiple pipelines in order to increase the number of instructions being processed concurrently. As the available clock frequency increases in microprocessors, the number of pipeline stages for a microprocessor are also increasing. Consequently, the number of active instructions within a pipeline that are in various stages of execution also increases. For example, the number of clock cycles between the time a load instruction is issued until the time a cache hit is returned for the load instruction has increased significantly with the increase in pipeline stages.
while these advancements in microprocessor clock frequency provide substantial enhancement of performance, the increase in pipeline stages causes undesirable complexity when utilizing a conventional method for speculative execution. Therefore, for a deep-pipelined microprocessor, a method is still needed for a microprocessor to forgo results computed by speculatively executed instructions and to restore the microprocessor to a particular state prior to the point when the speculative execution starts. For example, when a load instruction is executed, but a cache hit is not returned, any instructions speculatively issued after the load instruction must be aborted until the data can be retrieved from storage. In improving the performance of the microprocessor, there must be an issuance of subsequent instructions that depend on the load instruction so that if the load instruction returns a cache hit, then the latency between the load instruction and dependent instructions is minimized. However, while it is desirable to minimize the latency for cache hits, the method of minimizing should also minimize latency when there is not a cache hit.
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide an improved method and system for speculatively issuing instructions within a data processing system.
It is yet another object of the present invention to provided an improved method and system for speculatively issuing instructions within a data processing system which are dependent upon data from previously executed instructions for which a result is expected after n clock cycles.
The foregoing objects are achieved as is now described. A method and system for speculatively issuing instructions which are dependent upon results from execution of other instructions is provided. Instructions are speculatively issued, dependent upon a result from execution of a primary instruction, wherein the speculatively issued instructions are issued after execution of the primary instruction. N clock cycles are tracked after execution of the primary instruction, wherein the result from execution of said primary instruction is expected within n clock cycles. Execution of any speculatively issued instructions which are dependent upon the primary instruction is cancelled if the result is not returned from execution of the primary instruction within n clock cycles, such that for primary instructions for which the result is returned within the expected n clock cycles any speculatively issued instructions dependent upon said result are executed with increased efficiency.